BEIJING — In a development that underscores both the ingenuity and the severe constraints facing China’s domestic semiconductor sector, researchers at the Institute of Microelectronics of the Chinese Academy of Sciences (IMECAS) have successfully developed an experimental process flow for building stacked-nanosheet gate-all-around (GAA) transistors. Utilizing mature immersion deep ultraviolet (DUV) lithography rather than the restricted extreme ultraviolet (EUV) systems monopolized by Western-aligned supply chains, IMECAS has reportedly demonstrated functional devices.
According to reports from DigiTimes, this experimental workflow is engineered to pave the way for eventual adoption by domestic Chinese foundries aiming to produce 3nm-class and smaller process technologies. However, independent analysts and industry experts urge caution, noting that while the milestone proves theoretical viability, a vast chasm remains between demonstrating a single functional architecture in a laboratory setting and scaling a reliable, high-yield commercial manufacturing line.
Main Facts
The core of the announcement centers on IMECAS’s workaround for the ongoing geopolitical restrictions prohibiting the export of advanced EUV lithography machines to China.
- The Technology: IMECAS has fabricated stacked-nanosheet gate-all-around (GAA) transistors—the critical transistor architecture required for sub-5nm and 3nm semiconductor manufacturing.
- The Lithography Limitation: Unlike global industry leaders such as TSMC, Samsung, and Intel, who rely on ASML’s EUV scanners to pattern sub-3nm features directly, the IMECAS workflow achieves these results using immersion DUV lithography.
- The Multipatterning Burden: Utilizing DUV for sub-3nm nodes necessitates complex, multi-exposure techniques such as Self-Aligned Quadruple Patterning (SAQP) or multi-patterning immersion lithography (MPIL), which drastically increase mask counts, cycle times, and defect densities.
- Current Status: While IMECAS has successfully produced functional prototype devices, the institute has withheld critical geometrical parameters—such as nanosheet width, height, and gate pitch—preventing a direct technical comparison with commercial 3nm offerings from global foundries. Furthermore, the workflow remains an exploratory fabrication sequence rather than a fully realized process design kit (PDK) or commercial manufacturing line.
Chronology of Semiconductor Evolution and China’s GAA Pursuit
To understand the weight of the IMECAS breakthrough, it is necessary to examine the historical trajectory of transistor scaling and the compounding bottlenecks faced by China’s domestic chip ecosystem.
The Shift to FinFET and GAA (2010s–2020s)
For decades, planar MOSFET transistors formed the backbone of the computing industry. As scaling hit the 22nm and 14nm walls, planar designs suffered from severe short-channel effects, leading to current leakage and power inefficiencies.
- The FinFET Era: Around 2012, the industry transitioned to Fin Field-Effect Transistors (FinFETs), wrapping the gate around three sides of a silicon "fin." This architecture sustained scaling down to the 7nm and 5nm nodes.
- The GAA Nanosheet Era: To push past 5nm toward 3nm and 2nm, FinFETs ran out of geometric steam. The industry shifted to Gate-All-Around (GAA) architectures, where the gate material completely surrounds the channel (often built as horizontal stacked nanosheets), maximizing electrostatic control and minimizing leakage.
Export Controls and the Pivot to DUV (2019–Present)
- October 2019: Under pressure from the United States, the Dutch government blocked ASML from shipping its NX:3400B and later EUV systems (Twinscan NXE series) to Chinese entities like SMIC.
- October 2022 / October 2023: The U.S. Bureau of Industry and Security (BIS) tightened export controls, expanding restrictions to advanced immersion DUV systems (such as the TWINSCAN NXT:2000i series and above) and severely curtailing the export of advanced EDA software, materials, and equipment to Chinese fabs.
- Late 2023: Reports surfaced of Huawei and SMIC producing a 7nm-class processor (the Kirin 9000s) using advanced immersion DUV and aggressive multi-patterning techniques, proving that Chinese entities could stretch DUV beyond its conventional limits, albeit at a steep economic cost.
- 2024–2026 (Present): IMECAS steps into the spotlight by shifting focus from 7nm FinFET optimizations to next-generation 3nm-class GAA stacked nanosheets, attempting to leapfrog or match Western architectural milestones using constrained hardware.
Supporting Data and Technical Analysis
Building GAA nanosheets without EUV is a monumental engineering hurdle. To evaluate IMECAS’s achievement, semiconductor metallurgists and process engineers look at several key metrics: pitch scaling, overlay accuracy, and defect density.
The DUV vs. EUV Resolution Dilemma
Immersion DUV lithography operates at a 193nm wavelength. Utilizing argon fluoride (ArF) light sources, the theoretical resolution limit of DUV without complex optical proximity correction and multi-patterning is roughly 38nm to 40nm half-pitch.
By contrast, EUV systems operate at a 13.5nm wavelength, allowing complex features to be printed in a single exposure pass. When IMECAS uses DUV to target features sizing down to the 3nm class—where gate pitches shrink below 45nm and contacted poly pitches drop below 48nm—they must rely on multi-patterning techniques:
| Metric / Parameter | EUV-Based Approach (TSMC/Samsung/Intel) | DUV Multi-Patterning Approach (IMECAS Experimental) |
|---|---|---|
| Primary Lithography Tool | ASML NXE Series (13.5nm) | ASML/Domestic DUV Immersions (193nm) |
| Mask Count per Layer | Low (Single exposure for critical layers) | Extremely High (SAQP / LELE / Self-Aligned Block) |
| Cycle Time | Days per wafer lot | Weeks per wafer lot |
| Overlay Error Risk | Low to Moderate | High (Cumulative edge placement error) |
| Yield Potential | High (Commercialized) | Low (Research/Experimental phase) |
The Mechanics of Stacked-Nanosheet GAA
In an IMECAS-style stacked nanosheet device, silicon and silicon-germanium (SiGe) epitaxial layers are grown in alternating superlattices.
- Superlattice Growth: Epitaxial deposition of alternating Si and SiGe layers on a silicon substrate.
- Fin Patterning & Etching: Using DUV lithography and hard masks to cut vertical fins through the superlattice.
- Inner Spacer Formation: Recessing the SiGe sacrificial layers selectively while leaving the silicon nanosheets intact.
- Gate Wrap-Around: Depositing high-k metal gate (HKMG) materials to completely envelop each suspended silicon nanosheet.
While IMECAS has proven it can execute this sequence using DUV-patterned hard masks, the physical tolerances required to ensure uniform nanosheet thickness across a 300mm wafer are staggering. Without publishing critical dimensions (such as sheet thickness variations of less than 1 angstrom), industry observers remain skeptical about whether these experimental devices can maintain performance consistency at scale.
Official Responses and Industry Perspectives
The announcement has triggered widespread discussion across global semiconductor forums, macroeconomic think tanks, and domestic Chinese technology circles.
Industry Skepticism: Lab vs. Fab
Prominent semiconductor analysts emphasize the vast gulf between demonstrating a functional physics artifact in a cleanroom and manufacturing billions of reliable transistors on a commercial wafer.
"Demonstrating a functional GAA device is an important academic and technical proof-of-concept," noted a senior foundry engineer speaking on condition of anonymity. "However, building a research chip is not a defined process flow, and a defined process flow is light-years away from a manufacturable 3nm process. Without EUV, the cost of multi-patterning eats away all economic viability."
The Domestic Drive for Self-Sufficiency
Conversely, state-backed media and domestic Chinese researchers view the IMECAS breakthrough through the lens of strategic resilience. Deprived of foreign EUV equipment, Chinese research institutes are effectively rewriting the rulebook on how Moore’s Law can be sustained under economic and technological blockades.
The Chinese Academy of Sciences has increasingly prioritized indigenous semiconductor instrumentation, advanced materials, and novel etching chemistries to offset the missing hardware links in the lithography chain. For Beijing, the IMECAS milestone serves as tangible evidence that indigenous R&D can bypass foreign choke points, even if the timeline to commercialization remains protracted.
Implications for Global Competitiveness and Geopolitics
The implications of IMECAS’s experimental GAA workflow ripple across global supply chains, international trade policy, and the future trajectory of the semiconductor market.
1. Economic Viability and Yield Realities
Even if Chinese foundries eventually adopt the IMECAS DUV-GAA workflow to produce commercial chips, economic realities will dictate their market penetration. Multi-patterning immersion DUV exponentially increases manufacturing costs. Wafer costs could skyrocket, making chips produced via this method uncompetitive on price against products from TSMC or Samsung, unless heavily subsidized by state funds. Consequently, these chips are likely to find their primary deployment in state-supported sectors—such as military hardware, aerospace, high-performance computing, and sovereign AI infrastructure—where cost is secondary to security and availability.
2. Reinforcement of Export Controls
The success of IMECAS in pushing DUV to its absolute limits will likely be scrutinized closely by policymakers in Washington, Brussels, and The Hague. Rather than discouraging Western restrictions, such technological workarounds may fuel debates over whether to further tighten controls on mature-node equipment, cleaning tools, metrology systems, and chemical precursors. U.S. and allied regulators will evaluate whether loopholes in DUV oversight allow Chinese entities to gradually build the foundational knowledge base required to eventually manufacture domestic EUV alternatives.
3. Acceleration of Indigenous Equipment Ecosystems
Perhaps the most significant long-term implication is the pressure placed on China’s domestic equipment manufacturers—such as Advanced Micro-Fabrication Equipment Inc. (AMEC) and Shanghai Micro Electronics Equipment (SMEE). To turn IMECAS’s experimental DUV GAA flow into a viable commercial reality, Chinese equipment makers must drastically improve overlay precision, etch selectivity, and metrology speeds. The success of the IMECAS research pipeline acts as a bellwether, dictating engineering specifications for domestic tool vendors striving to close the generational gap with ASML, Applied Materials, and Lam Research.
Conclusion
The announcement that IMECAS has successfully fabricated functional gate-all-around stacked nanosheet transistors using immersion DUV lithography marks a fascinating chapter in modern semiconductor history. It illustrates human ingenuity under intense geopolitical pressure, demonstrating that physical laws can be stretched through sheer engineering tenacity.
Yet, sober realism must prevail. The distance between a laboratory demonstration of a novel transistor architecture and a high-yield, economically viable 3nm commercial foundry node is vast. As IMECAS continues to refine its experimental process flow, the global semiconductor industry watches closely—not just to see if China can conquer the physics of sub-3nm scaling without EUV, but at what economic and industrial cost that victory will be achieved.
